1. Field of the Invention
The present invention relates to a booster circuit used for a semiconductor memory device etc.
2. Description of the Related Art
A semiconductor memory device, for example, a flash memory, is provided with a voltage booster circuit which boosts the reference power source voltage, for example, 5 V, to a high voltage of 12 to 20 V and a negative high voltage of -6 V to -20 V and supplies the resultant voltage to a predetermined functional block.
FIG. 1 is a circuit diagram showing a general voltage booster circuit of a positive voltage for obtaining an output of 20 V by boosting a power source voltage of for example +5 V.
In FIG. 1, V.sub.cc denotes a power source voltage; 1 denotes a voltage feeding line of the power source voltage; NT.sub.0 to NT.sub.4 (5 to 9) denote n-channel MOS (metal oxide semiconductor) transistors (hereinafter, referred to as nMOS transistors); C.sub.1 to C.sub.4 (17 to 20) denote capacitors for pumping; ND.sub.0 to ND.sub.4 (11 to 15) denote nodes; T.sub.OUT (21) denotes an output terminal; V.sub.OUT denotes an output signal; and .phi..sub.1 (2) and .phi..sub.1-- (3) denote clock signals of mutually complementary levels; respectively.
The nMOS transistors NT.sub.0 to NT.sub.4 (5 to 9) are connected in a form of cascade, the drain of the nMOS transistor NT.sub.0 (5) is connected to the line i of the power source voltage V.sub.cc, and the source of the nMOS transistor NT.sub.4 (9) is connected to the output terminal T.sub.OUT (21).
The node ND.sub.0 (11) is constituted by a point of connection between the line 1 of the power source voltage V.sub.cc and the nMOS transistor NT.sub.0 (5); the node ND.sub.1 (12) is constituted by the point of connection between the source of the nMOS transistor NT.sub.0 (5) and the drain of the nMOS transistor NT.sub.1 (6); the node ND.sub.2 (13) is constituted by the point of connection between the source of the nMOS transistor NT.sub.1 (6) and the drain of the nMOS transistor NT.sub.2 (7); the node ND.sub.3 (14) is constituted by the point of connection between the source of the nMOS transistor NT.sub.2 (7) and the drain of the nMOS transistor NT.sub.3 (8); and the node ND.sub.4 (15) is constituted by the point of connection between the source of the nMOS transistor NT.sub.3 (8) and the drain of the nMOS transistor NT.sub.4 (9); respectively.
The nMOS transistors NT.sub.0 to NT.sub.4 (5 to 9) are "diode-connected", with the drains and gates being connected. Namely, the node ND.sub.0 (11) and the gate of the nMOS transistor NT.sub.0 (5) are connected; the node ND.sub.1 (12) and the gate of the nMOS transistor NT.sub.1 (6) are connected; the node ND.sub.2 (13) and the gate of the nMOS transistor NT.sub.2 (7) are connected; the node ND.sub.3 (14) and the gate of the nMOS transistor NT.sub.3 (8) are connected; and the node ND.sub.4 (15) and the gate of the nMOS transistor NT.sub.4 (9) are connected.
The nodes ND.sub.1 to ND.sub.4 (12 to 15) are connected to the pumping capacitors C.sub.1 to C.sub.4 (17 to 20), respectively; the capacitors C.sub.1 (17) and C.sub.3 (19) are connected to an input line of the clock signal .phi..sub.1 (2); and the capacitors C.sub.2 (18) and C.sub.4 (20) are connected to the input line of the clock signal .phi..sub.1-- (3).
The clock signals .phi..sub.1 (2) and .phi..sub.1-- (3) are complementary signals which alternately take the power source voltage V.sub.cc level and "0" V level in a predetermined cycle.
Accordingly, when the clock signal .phi..sub.1 is at the V.sub.cc level, the nodes ND.sub.1 (12) and ND.sub.3 (14) are boosted (raised up) by the amount of for example the voltage V.sub.c by the capacitance connection of the capacitors C.sub.1 (17) and C.sub.3 (19). At this time, since the clock signal .phi..sub.1-- (3) is at "0" V, the nodes ND.sub.2 (12) and ND.sub.4 (15) are pulled down (lowered in level).
On the other hand, when the clock signal .phi..sub.1 (2) is at "0" level, the nodes ND.sub.1 (12) and ND.sub.3 (13) are lowered in level. At this time, since the clock signal .phi..sub.1-- (3) is at the V.sub.cc level, the nodes ND.sub.2 (13) and ND.sub.4 (15) are raised up by the amount of the voltage V.sub.c by the capacitance connection of the capacitors C.sub.2 (18) and C.sub.4 (20).
FIG. 3 is a waveform diagram showing the process of boosting of the nodes ND.sub.1 (12) and ND.sub.2 (13) in the positive booster circuit of FIG. 1.
As shown in FIG. 3, in the booster circuit of FIG. 1, by inputting the clock signals .phi..sub.1 (2) and .phi..sub.1-- (3) taking complementary levels to the pumping capacitors C.sub.1 to C.sub.4 (17 to 20), a current is passed toward the output side, so that the charges of the capacitors C.sub.1 to C.sub.4 (17 to 20) are sequentially transported.
More specifically, in the period a shown in the diagram, the clock signal .phi..sub.1 (2) is at the V.sub.cc level and input to the capacitor C.sub.1 (17), and the clock signal .phi..sub.1-- (3) is at the "0" V and input to the capacitor C.sub.2 (18).
Accordingly, the node ND.sub.1 (12) is boosted (raised) by the amount of the voltage V.sub.c by the capacitance connection of the capacitor C.sub.1 (17), while the node ND.sub.2 (13) is lowered by the amount of the voltage V.sub.c.
Along with the boosting of the node ND.sub.1 (12), the voltage v.sub.c is applied to the nMOS transistor NT.sub.1 (6), and therefore a current i.sub.1 is passed toward the node ND.sub.2 (13) of the next stage, and the charges of the capacitor C.sub.1 (17) are transported to the node ND.sub.2 (13).
Along with this, the voltage V.sub.2 of the node ND.sub.2 (13) slightly rises at the point of time at which the period a is ended.
In the next period b, the clock signal .phi..sub.1 (2) is input to the capacitor C.sub.1 (17) at "0" V, and the clock signal .phi..sub.1-- (3) is input to the capacitor C.sub.2 (18) at the V.sub.cc level.
Accordingly, the capacitance connection of the capacitor C.sub.1 (17) is not carried at the node ND.sub.1 (11). This is lowered by the amount of the voltage V.sub.c, and the node ND.sub.2 (13) is raised by the amount of the voltage V.sub.c. Accordingly, the voltage V.sub.2 at the node ND.sub.2 (13) becomes the next value obtained by adding the amount of the rising voltage (+).alpha. by the inflow of the current i.sub.1 : EQU V.sub.2 =V.sub.c +.alpha. (1)
By this, the nMOS transistor NT.sub.1 (6) becomes the OFF state and the current i.sub.1 no longer flows, so that the charges are transported to the node ND.sub.2 (12) of the next stage, which means that the voltage V.sub.2 of the node ND.sub.2 (12), that is, the source voltage of the nMOS transistor NT.sub.1 (6), rises.
Along with the boosting of the node ND.sub.2 (13), the voltage (V.sub.c +.alpha.) is applied to the gate of the nMOS transistor NT.sub.2 (7), and therefore the current i.sub.2 flows toward the node ND.sub.3 (14) of the next stage, and the charges of the capacitor C.sub.2 (18) are transported to the node ND.sub.2 (12).
Along with this, the voltage of the node ND.sub.3 (14) further rises at the point of time when the period b is ended.
An operation similar to the above is repeated, and the predetermined high voltage output V.sub.OUT appears at the output terminal T.sub.OUT (21).
Where the charges are transported to the node ND.sub.2 (13) of the next stage via for example the nMOS transistor NT.sub.1 (6) in this booster circuit, that is, when the current i.sub.1 flows, the source voltage of the nMOS transistor NT.sub.1 (6)=drain voltage of the nMOS transistor NT.sub.1 (6)=gate voltage of the nMOS transistor NT.sub.1 (6)=V.sub.1 stands, and therefore it is necessary to satisfy the following relationship: EQU V.sub.1 -V.sub.2 &gt;V.sub.th ( 2)
Here, V.sub.th indicates the threshold voltage of the nMOS transistor.
Accordingly, a condition with which the current i.sub.1 flows and the charges are transported becomes as follows if the voltage at which the nodes ND.sub.1 (12) and ND.sub.2 (13) are raised/lowered by the capacitors C.sub.1 (17) and C.sub.2 (18) as mentioned above is V.sub.c : EQU (V.sub.1 +V.sub.c)-(V.sub.2 -V.sub.c)&gt;V.sub.th(1)
Namely, EQU 2V.sub.c -V.sub.th(1) &gt;V.sub.2 -V.sub.1 ( 3)
A circuit of FIG. 1 satisfying this condition can sequentially shift the charges of the capacitors C.sub.1 to C.sub.4 (17 to 20) to the output terminal T.sub.OUT (21) through the node ND.sub.1 (11) to the node ND.sub.4 (15) using the complementary clock signals .phi..sub.1 (2) and .phi..sub.1-- (3) and can boost the power source voltage V.sub.cc to the desired voltage.
FIG. 4 is a circuit diagram showing a negative booster circuit for obtaining a negative high voltage.
The point of difference of this circuit from the positive booster circuit of FIG. 1 resides in a fact that pMOS transistors PT.sub.0 to PT.sub.4 (40 to 44) are used in place of the nMOS transistors NT.sub.0 to NT.sub.4 (5 to 9) and in that the node ND.sub.10 (31) is grounded in place of the power source voltage V.sub.cc.
In the case of this negative booster circuit, the current flows from the output side toward the ground, a charge shift is performed along with the input of the clock signals .phi..sub.2 (52) and .phi..sub.2-- (53) to the capacitors C.sub.11 to C.sub.14 (47 to 50), and the negative voltage is gradually accumulated in the output terminal T.sub.OUT (36), so that the negative high voltage output V.sub.OUT is obtained.
The threshold voltage V.sub.th of the MOS transistor is susceptible to the influence of a so-called back bias effect wherein the threshold voltage is increased when the source voltage rises.
Here, when it is assumed that the threshold voltage V.sub.th when the substrate voltage=source voltage=0 V is "0.8 V", the threshold voltage V.sub.th when the source voltage is 10 or so volts becomes about 2 V. For this reason, there is a problem in that as the number of boosting stages is increased and the voltage becomes higher, so the efficiency per stage is degraded.
In the above-mentioned equation (3), when it is assumed that there is no back bias effect and V.sub.c =4 V, the following stands: EQU V.sub.2 -V.sub.1 &lt;8-0.8 V=7.2 V
but when the threshold voltage V.sub.th becomes equal to 2 V by the back bias effect, the following stands: EQU V.sub.2 -V.sub.1 &lt;8-2=6 V
When it is assumed that the operation must be performed even at 2.5 V so as to guarantee the operation of the power source voltage 3.0 V, if V.sub.c =2 V, the following comes to stand: EQU V.sub.2 -V.sub.1 &lt;4-2=2 V
Conventionally, so as to avoid the influence by this back bias effect, a countermeasure in which the threshold voltage V.sub.th of the transistors of a part of a higher level of the stages, for example, nMOS transistors NT.sub.3 (8) and NT.sub.4 (9) Of FIG. 1, is lowered and brought to 0 V has been carried out. By taking this countermeasure, however, there is a problem in that the manufacturing process becomes cumbersome etc.
Moreover, there has also been proposed a voltage booster circuit constituted so that the gate voltage is raised by the amount of increase of the threshold voltage V.sub.th by the back bias effect as shown in FIGS. 11 and 13 of the document entitled the IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 27. NO. 11, 1992, pp 1540 to 1546.
FIG. 5 is a circuit diagram showing the positive booster circuit disclosed in FIG. 13 of this document.
This circuit is constituted in that, in addition to the circuit of FIG. 1, the capacitors CG.sub.1 to CG.sub.4 (87 to 90) for boosting the gates are connected to the gates of the respective nMOS transistors NT.sub.20 to NT.sub.23 (12 to 75); the nMOS transistors NTG.sub.0 to NTG.sub.3 (61 to 64) are inserted and connected between the respective nodes ND.sub.20 to ND.sub.23 (66 to 69) and the gates of the nMOS transistors NT.sub.20 to NT.sub.23 (72 to 75); and the gates of the respective nMOS transistors NTG.sub.0 to NTG.sub.3 (61 to 64) are connected to the nodes ND.sub.21 to ND.sub.24 (67 to 70) of the one later stage.
So as to actuate this circuit, four phase clock signals .phi..sub.5 to .phi..sub.8 set up at the timing as shown in FIG. 6 are input to the respective capacitors C.sub.21 to C.sub.2 (93 to 96) and CG.sub.1 to CG.sub.4 (87 to 90) at a predetermined timing.
Specifically, the clock signal .phi..sub.7 is input to the node pumping capacitors C.sub.21 and C.sub.23, the clock signal .phi..sub.5 is input to the capacitors C.sub.22 (93) and C.sub.24 (96), respectively, the clock signal .phi..sub.6 is input to the gate pumping capacitors CG.sub.1 (87) and CG.sub.3 (89), and the clock signal .phi..sub.8 is input to the capacitors CG.sub.2 (89) and CG.sub.4 (90), respectively.
Here, for simplification, a case where for example the clock signal .phi..sub.5 is input to the capacitor C.sub.22 (94) at the V.sub.cc level and the clock signal .phi..sub.7 is input to the capacitor C.sub.23 (95) at "0" V is assumed.
In this case, the node ND.sub.22 (68) is in the boosting state, and the node ND.sub.23 (69) is in the lowered state. Accordingly, the gate voltage of the nMOS transistor NTG.sub.2 (63) is at the same level as the level of the node ND.sub.23 (69), and therefore the nMOS transistor NTG.sub.2 (63) is retained in the OFF state.
In this state, when the clock signal .phi..sub.6 becomes the V.sub.cc level, by the capacitance connection of the capacitor CG.sub.3 (89), the gate voltage of the nMOS transistor NT.sub.22 (74) is raised to a level that can cancel the back bias effect.
For this reason, the charges of the capacitor C.sub.22 (94) are transferred well to the node ND.sub.23 (69) via the nMOS transistor NT.sub.22 (68).
Next, when the clock signal .phi..sub.5 is switched to "0" V and the clock signal .phi..sub.8 is switched to the V.sub.cc level, the node ND.sub.22 is lowered, and the node ND.sub.23 is boosted. At this time, the clock signal .phi..sub.6 is switched to "0" V.
Since the node ND.sub.23 (69) is in the boosting state, also the gate voltage of the nMOS transistor NTG.sub.2 (63) becomes the high level, and the nMOS transistor NTG.sub.2 (63) becomes the ON state. By this, the node ND.sub.22 (68) and the node NG.sub.2 (83) on the gate side of the nMOS transistor NT.sub.22 (74) become the same potential, and therefore a current is not passed from the node ND.sub.23 (69) to the node ND.sub.22 (68).
However, the circuit of FIG. 5 has the following problem.
Namely, since a voltage higher than the output voltage is applied on the gate of the nMOS transistor, it is necessary to increase the gate voltage resistance by that amount in consideration of the transition state etc. Accordingly, processing for making the gate oxide film thicker is necessary.
Also, since four phase clock signals .phi..sub.5 to .phi..sub.8 are used, the clock generation circuit becomes complex, and since the gate pumping capacitors CG.sub.1 to C.sub.4 (87 to 90) are necessary, an increase of the surface area of the circuit and power consumption is induced.
Since the ratio between the pumping capacitors of the respective nodes and the parasitic capacitance becomes bad, operation with slow voltage source is difficult. Namely, the maximum voltage for boosting the gate is the power source voltage times the above-described capacitance ratio, and therefore 2.0 V is the limit even if the capacitance ratio is brought to 80% where the power source voltage is 2.5 V, and thus it is not possible to cancel the amount of increase of the threshold voltage V.sub.th by the back bias effect.
Also, it is a so-called non-overlap type four phase pulse, and therefore it is not possible to raise the frequency that high, which consequently lowers the current capability.